This disclosure relates generally to dynamic power management techniques implemented for semiconductor chips, and particularly to novel system and method for estimating dynamic power usage at a sub-component level when operating under workload conditions.
Current approaches to dynamic power estimation include use of hardware performance counters. This requires dedicated hardware counters, software techniques to access those counters, and algorithms to map counter readings to power estimates in semiconductor Integrated Circuits (ICs or chips).
There are currently known techniques and methods for runtime power monitoring in high-end processors. For example, use of accurate fine-grained processor power proxies is well established for obtaining chip dynamic power estimates.
Other approaches to dynamic power estimation include estimating whole chip power using activity counters, voltage, and frequency measurements.
Other known solutions include using temperature and voltage measurements to estimate leakage in the chips. Other solutions use real-time voltage, temperature, and pre-determined constants to compute leakage power. The constants are used to scale the leakage power according to using many temperature points that represent unequal (in terms of leakage) parts of the chip.
Still other techniques teach use of a pre-populated look-up table indexable by temperature and voltage to find a leakage power entry. Use of such table is triggered on device reset to avoid overuse of a multiply accumulator. Further teachings include using an on-chip micro or off-chip micro to compute the leakage equation. Constants are typically determined at manufacturing time.
Further teachings in the art include measuring voltage, measuring temp, and multiplying associated scalars with a reference leakage power value determined at manufacturing time to determine real-time leakage.
Further, there are currently implemented so-called “Power Proxies” that are chip-level and core-level power proxies where hardware (HW) is used to compute activity per-core (HW computes activity proxy). Such hardware includes as much as 50 activity counters in IBM's POWER 7+ processor's architecture, and the technique includes periodically tracking changes in voltage, frequency, temperature, and workload activity.
Further systems obtain leakage power measurements at manufacturing time, e.g., measured voltage and measured temperature, and these measurements are used to find run-time leakage.
Other techniques include estimating computer power by using an instruction trace and model of instruction power (simulation).
A major problem for these prior art devices is that they are hardware intensive and entirely accurate, especially as they omit leakage estimation at workload conditions, i.e., when executing or running.
It would be desirable to provide a system and method to enable accurate post-silicon leakage power characterization at very high temperatures, and at a much wider range of temperature and voltages, without the need for costly tester/heating infrastructure.